The present invention relates to a method and/or architecture for implementing bus interface protocols generally and, more particularly, to a method and/or architecture for real-time I/O processor for implementing bus interface protocols.
Conventional approaches for implementing bus interfaces are (i) protocol-specific interfaces and (ii) user programmable interfaces. Protocol-specific interfaces allow a circuit to connect to one and only one specific type of interface. Examples of such protocol specific designs are the interface to the P1284 printer parallel bus, EPP interface, ATAPI interface, ISA interface, etc.
Referring to FIGS. 1a-c, block diagrams of a circuit 10, a circuit 20 and a circuit 30 for implementing a protocol specific approach between a Universal Serial Bus (USB) interface and other specific type interfaces are shown. The circuit 10 is a block diagram illustrating a USB interface to an EPP interface. The circuit 20 is a block diagram illustrating a USB interface to an ATAPI interface. The circuit 30 is a block diagram illustrating a USB interface to an ISA interface. Implementing a separate circuit for each interface is undesirable.
The protocol-specific approaches 10, 20 and 30 are limited to a specific type of interface. The protocol-specific approaches can limit the marketability and relevancy of a product. The inherent lack of flexibility in the protocol-specific approach entails manufacturer risks, since marketing requirements and bus standards can change rapidly.
Conventional user-programmable interfaces allow a user to specify a fixed number of wait-states before attempting to interface with another device. Programming the wait state enables a handshake xe2x80x9creadyxe2x80x9d signal of the user-programmable interface. User-programmable interfaces require additional intervention (i.e., by the user) and can be difficult to program. Additionally, the user-programmable interfaces do not allow the flexibility, sophistication, or functionality required to implement complex interface signaling, because of the user-programmed fixed number of wait states.
Referring to FIG. 2, a circuit 40 illustrating a conventional implementation for interconnecting a data resource 42 to an external logic circuit 44 is shown. The data resource 42 is shown as a FIFO memory. The FIFO 42 can be self-contained or incorporated into an interface circuit (i.e., a microprocessor or an application specific integrated circuit (ASIC)) 46.
Data is transferred between the FIFO 42 and the external logic circuit 44 using a data bus DATA_BUS and a set of control signals CLOCK, RD, WR and FLAGS. The external logic circuit 44 generates the read signal RD and the write signal WR while responding to the flag signal FLAGS. The flag signal FLAGS is generated by the FIFO 42 and indicates a condition of the FIFO 42. For example, the signals FLAGS can indicate that the FIFO 42 is full and cannot be written to or that the FIFO 42 is not empty and can be read. The circuit 40 can implement the read signal RD and the write signal WR as direct data signals, providing an asynchronous interface. Additionally, the circuit 40 can allow the external logic circuit 44 to provide an optional clock signal CLOCK which is enabled in response to the read signal RD and the write signal WR, providing a synchronous interface.
The circuit 40 is a master-slave device arrangement. The master is the external logic circuit 44 and the slave is the data source 42. The master external logic circuit 44 provides the control signals RD and WR and/or optionally CLOCK for the interface circuit 46 and/or the data source 42. Additionally, the master external logic circuit 44 responds to the feedback signal FLAGS. The interface circuit 46 and/or the data source 42 functions as a slave in response to the master external logic circuit 44. The slave interface circuit 46 and/or the data resource 42 responds directly to the signals RD and WR and/or optionally CLOCK received from the master external logic circuit 44.
Referring to FIG. 3, a conventional implementation of four FIFOs 42a-42n embedded in a controller chip is shown. The FIFOs 42a-42n function as conventional slave devices as previously described in connection with the interface circuit 46 and/or the data resource 42 of FIG. 2. The FIFO clock and strobe signals are supplied by a master external interface (i.e., the external logic circuit 44). The conventional slave FIFOs 42a-42n respond directly to the master external logic control signals. Additionally, waveforms illustrating asynchronous and synchronous operation of the conventional slave FIFOs 42a-42n are shown as previously described in connection with FIG. 2.
One aspect of the present invention concerns a circuit that may be configured to store data and interface with an external device. The circuit may provide one or more control signals to the external device.
Another aspect of the present invention concerns a circuit configured to store data and provide one or more control signals to an external device. At least one of the one or more control signals comprising a programmable clock signal.
Another aspect of the present invention concerns a method for providing a generic interface configured to control an external device comprising the steps of (A) reading an instruction and (B) performing an operation comprising either (i) waiting a predetermined number of clock periods or (ii) branching in response to one or more signals received on a pin.
Another aspect of the present invention concerns a method for providing a generic interface configured to control an external device comprising the steps of (A) receiving a clock signal and (B) progressing to a next state based on a current state and one or more input signals in a single cycle of the clock signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for implementing an interface that may (i) allow a single processor architecture to be implemented for a number of design specific devices, (ii) allow efficient implementation of multiple industry-standard protocols, (iii) allow customer-specific interfaces, (iv) allow a processor-based solution to implement changing and possibly future unknown standards, (v) minimize a risk of interface errors, (vi) control a data source (e.g., a FIFO memory), (vii) develop a set of interface control signals and respond to a set of interface ready signal, (viii) operate at a higher rate (e.g., speed) than standard microprocessor input/output systems, (ix) allow decisions to be made and output to be changed once per clock cycle, (x) be programmable, (xi) be controlled by instructions in a control store, and/or (xii) allow operation to be suspended by interrupting a processor and later resumed by the processor asserting an internal ready signal.